The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a flash memory device which can minimize the interference phenomenon between adjacent floating gates and a method of manufacturing the same.
Recently, in the manufacturing of flash memory devices, the spaces in which a unit active region and a unit field region will be formed are continuously being reduced as the level of integration is increased. As the dielectric film including the floating gate and the control gates are formed within the narrow active space, the inter-gate distance becomes narrow and the interference phenomenon becomes more problematic.
FIG. 1 is a cross-sectional view of a general flash memory device and illustrates a method of manufacturing a flash memory device to which self-aligned Shallow Trench Isolation (STI) is applied.
Referring to FIG. 1, a tunnel oxide film 11 and a first polysilicon film 12 are sequentially formed over a semiconductor substrate 10. The first polysilicon film 12 and the tunnel oxide film 11 are selectively etched by an etch process employing an isolation mask. The semiconductor substrate 10 is then etched using the first polysilicon film 12 as a mask, thus forming trenches.
An insulating film, such as a High Density Plasma (HDP) oxide film, is formed over the trenches and the first polysilicon film 12 on the entire structure so that the trenches are filled. The insulating film is polished by Chemical Mechanical Polishing (CMP) to expose the top surface of the first polysilicon film 12, thereby forming isolation structures 13 within the trenches.
A second polysilicon film 14 is formed over the isolation structures 13 and the first polysilicon film 12. The second polysilicon film 14 is etched using a mask to form a floating gate with both the first polysilicon film 12 and the second polysilicon film 14. A dielectric film 15 and a conductive film 16 are sequentially formed over the floating gate and the isolation structures 13 and are then patterned using a mask, forming control gates over the isolation structure 13.
However, as semiconductor devices continue to become more integrated, the width of the isolation structure is made smaller. Accordingly, the distance between adjacent first polysilicon films is also reduced, resulting in an interference phenomenon.
Furthermore, the threshold voltage (Vt) of the semiconductor substrate is changed due to the interference phenomenon between the floating gates. As the interference phenomenon increases in the direction of the control gates, device characteristics are inevitably degraded. The interference phenomenon lowers the program speed of the flash cell and results in degraded quality.